Digital design : with an introduction to the verilog HDL, VHDL, and system Verilog 2026-02-15T21:24:27+03:00 DEBUG: VuFind\ILS\Driver\Folio: Token taken from global cache: eyJhbGciOiJIUzI1NiJ9.eyJzdWIiO... - Mano, M. Morris; Ciletti, Michael D. (Pearson, 2019)